(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for improving the short channel effect and the gate oxide reliability of CMOS devices by nitrogen plasma treatment before spacer deposition.
(2) Description of the Prior Art
Conventional methods of forming CMOS gate electrodes in or over an active device region of a semiconductor substrate are well known in the art. The active device region is typically defined by field oxide regions, which electrically isolate the active region of the substrate from the surrounding surface areas of the substrate.
Substrate conductivity in the active surface area is first established by providing n/p-well impurity implants into the active surface of the substrate. In fabricating a CMOS device, a layer of gate material such as polysilicon is formed over a layer of thin oxide that is formed over the active device region of the substrate. The polysilicon layer is then masked and both the exposed polysilicon and the underlying thin layer of oxide are etched to define a poly-silicon gate electrode that is separated from the substrate by the thin layer of gate oxide. A self-aligned implant of for instance N-type dopant then forms lightly doped diffusion (LDD) source/drain regions in the substrate as a first phase of forming the substrate N-type source/drain regions of the CMOS device. After the formation of for instance oxide sidewall spacers on the sidewalls of the polysilicon gate and of the gate oxide, a second N-type impurity implant is performed to set the conductivity of the gate region to a desired level and to complete the N+ source/drain regions of the gate electrode.
Contact surfaces of the gate electrode may then be salicided by depositing for instance a layer of titanium over the structure, more specifically over the exposed surfaces of the N+ source/drain regions and the gate electrode. The deposited titanium is annealed, thereby causing the titanium to react with the underlying N+ silicon of the substrate of the source/drain regions and the doped polysilicon gate to form titanium salicide over these surfaces.
The gate electrode is completed by forming a layer of dielectric material, typically silicon oxide, over the gate electrode. Contact openings are etched in the dielectric and a metallization layer is formed to provide contacts to the salicided surfaces of the source/drain regions and over the polysilicon gate.
Semiconductor device performance improvements require the reduction of device dimensions from which follows in increase in device density. As devices and the therefrom created circuits are scaled down to sub-0.25 μm dimensions for Ultra Large Scale Integrated (ULSI) technology devices, the quality of the spacers that are created over sidewalls of the gate electrode becomes increasingly more important in view of the increased demands of device insulation. Continued reduction in device dimensions imposes increased demands on the profile of the impurity implants, which results in the need to reduce the thermal cycle of the gate electrode.
During conventional processing steps for the creation of a gate electrode, specifically during the etch of the layer of gate material to create the gate electrode, the etch results in damage to the silicon substrate, which is exposed during the etch, and to sidewalls of the patterned and etched layer of gate material. To repair this damage, a step of re-oxidation is typically performed, this step removes the damage that has resulted from the etch of the layer of gate material. The need however to reduce the thermal budget during the creation of a gate electrode imposes the need to remove the re-oxidation step. This removal of the re-oxidation must be compensated for since the damage in the silicon substrate and the sidewalls of the etched layer of gate material must as yet be prepared. There is a need for the highlighted compensation and repair of etch induced damage.
U.S. Pat. No. 5,808,348 (Ito et al.) shows a nitrided gate oxide process.
U.S. Pat. No. 6,373,113 B1 (Gardner et al.) shows a nitrogenated gate structure and method.
U.S. Pat. No. 5,990,517 (Irino) discloses a process to introduce nitrogen into a gate dielectric.
U.S. Pat. No. 5,872,049 (Gardner et al.), U.S. Pat. No. 5,567,638 (Lin et al.) and U.S. Pat. No. 5,189,504 (Nakayama et al.) are related patents.